diff --git a/src/ext/equix/hashx/src/compiler_a64.c b/src/ext/equix/hashx/src/compiler_a64.c index 1b7081f537..2e286b3099 100644 --- a/src/ext/equix/hashx/src/compiler_a64.c +++ b/src/ext/equix/hashx/src/compiler_a64.c @@ -55,7 +55,7 @@ bool hashx_compile_a64(const hashx_program* program, uint8_t* code) { uint8_t* target = NULL; int creg = -1; EMIT(pos, a64_prologue); - for (int i = 0; i < program->code_size; ++i) { + for (size_t i = 0; i < program->code_size; ++i) { const instruction* instr = &program->code[i]; switch (instr->opcode) { diff --git a/src/ext/equix/hashx/src/program.c b/src/ext/equix/hashx/src/program.c index 1017d4070a..267ab5956a 100644 --- a/src/ext/equix/hashx/src/program.c +++ b/src/ext/equix/hashx/src/program.c @@ -678,7 +678,7 @@ bool hashx_program_generate(const siphash_state* key, hashx_program* program) { /* Calculate ASIC latency: Assumes 1 cycle latency for all operations and unlimited parallelization. */ - for (int i = 0; i < program->code_size; ++i) { + for (size_t i = 0; i < program->code_size; ++i) { instruction* instr = &program->code[i]; if (instr->dst < 0) continue; @@ -724,8 +724,8 @@ bool hashx_program_generate(const siphash_state* key, hashx_program* program) { static const char* x86_reg_map[] = { "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" }; void hashx_program_asm_x86(const hashx_program* program) { - int target = 0; - for (unsigned i = 0; i < program->code_size; ++i) { + size_t target = 0; + for (size_t i = 0; i < program->code_size; ++i) { const instruction* instr = &program->code[i]; switch (instr->opcode) { @@ -762,13 +762,13 @@ void hashx_program_asm_x86(const hashx_program* program) { break; case INSTR_TARGET: printf("test edi, edi\n"); - printf("target_%i: cmovz esi, edi\n", i); + printf("target_%i: cmovz esi, edi\n", (int)i); target = i; break; case INSTR_BRANCH: printf("or edx, esi\n"); printf("test edx, %i\n", instr->imm32); - printf("jz target_%i\n", target); + printf("jz target_%i\n", (int)target); break; default: UNREACHABLE;